Recently, the AI chip darling that submitted an IPO—Cerebras—has become a sensation in Silicon Valley.

Its chips, in small model scenarios, can achieve inference speeds up to 20 times that of H100; for ultra-large models (such as 400B parameters), the response speed of the Cerebras CS-3 system for a single user is about 2.4 times that of B200.
So how exactly does Cerebras do it? Will it become a NVIDIA killer?
We need to start from the essence of computing power evolution.
The evolution of AI computing power is shifting from “raw compute” to “communication and system architecture.” On this evolutionary path, Cerebras Systems offers a completely different answer: not optimizing distributed systems, but eliminating distribution as much as possible.
**1. Two approaches: eliminating communication vs optimizing communication**
Currently, AI computing architecture fundamentally follows two philosophies: one represented by NVIDIA:
Multi-chip (GPU), high-speed interconnect (NVLink / CPO), scale-out (horizontal expansion)
The other is Cerebras’ path: achieving the limit on a single chip (wafer-scale)
On-chip network replaces cross-node communication, scale-up (vertical expansion)
The core difference is: one addresses “how to connect more chips,” the other addresses “how to not need connections.”
**2. Why is this approach only now feasible?**
Wafer-scale is not a new concept; attempts date back to the 1980s, with commercial failures in the 1990s. The reasons are:
Yield cannot support it
Lack of fault-tolerance mechanisms
Software cannot support it
The industry thus reached a consensus: small dies + high yield + distributed systems.
Cerebras’ breakthrough lies in three simultaneous developments:
1) Engineering of fault-tolerance mechanisms
2) Maturity of on-chip networks
3) Matching AI workloads (high parallelism, strong synchronization, communication-driven)
The fundamental change is: shifting from “perfect hardware” to “fault-tolerant systems.”
**3. Performance comparison: single-point limit vs system scaling**
In terms of communication, the advantages and disadvantages of the two approaches are very clear:
1) On-chip communication
Cerebras: purely on-chip → lowest latency, lowest energy consumption
CPO: still involves optical-electrical conversion
→ Single-point efficiency: Cerebras is better
2) System scaling
Cerebras: once crossing chips → back to communication issues
CPO: bandwidth can be sustainably expanded
→ System capability: CPO is better
3) Power consumption structure
Cerebras: extremely high power consumption for a single machine, but communication is very efficient
GPU + CPO: single-point power consumption is controllable, overall system efficiency is more balanced
The conclusion is clear:
Cerebras wins at “single-machine limits,”
CPO wins at “system scale.”
**4. Suitable scenarios: who should use Cerebras**
The criteria can be simplified into three questions:
1) Is communication a bottleneck?
2) Can tasks be centralized?
3) Is the architecture regular?
Therefore, it is highly suitable for large model training (dense models), very long context windows, and some HPC tasks (PDEs, fluid dynamics, etc.)
These tasks share characteristics: strong coupling + high synchronization + high bandwidth.
It is partially suitable for large model inference (low concurrency), graph computing (when structure complexity reduces advantages).
Not suitable for CPU (general-purpose computing), high-concurrency inference, mobile/edge chips, real-time systems.
These systems share characteristics: irregularity / high concurrency / low latency.
**5. Will it become mainstream?**
Although Cerebras is extremely powerful in specific scenarios, it is unlikely to become mainstream because:
1) Physical constraints: power density; signal delay → fault-tolerance cannot solve these issues
2) Economics: higher yield for small dies; chiplet flexibility
3) Industry path: TSMC and others favor modular, multi-client reuse over ultra-large monoliths
4) Demand-side changes: inference accounts for a much higher proportion than training; multi-task, high concurrency are becoming mainstream
**6. The significance of Cerebras**
Rather than wafer-scale size being an important trend, it’s the fault-tolerant design philosophy that will be widely adopted.
Future developments may include chiplet-level fault tolerance and packaging-level rerouting.
The core change is that individual hardware no longer needs to be perfect; the system takes responsibility for fault mitigation.
Returning to the initial question: will Cerebras become NVIDIA’s “killer”?
The answer is already quite clear.
It indeed hits a soft spot in GPU architecture—communication. But industry choices are not binary; multiple technological breakthroughs will be adopted simultaneously: stronger interconnects, lower communication energy, higher system-level efficiency.
Therefore, a more accurate view is that Cerebras is not NVIDIA’s killer but a best practice for all chip companies to learn from.
Disclaimer: I hold the assets mentioned in this article. My views are biased and not investment advice. Investment risks are significant; proceed with extreme caution.
(Image: a Cerebras chip)